EP2S60F484C3N

Product Summary

The EP2S60F484C3N is a very high-density FPGA. The core of an enhanced configuration device is divided into two major blocks: a configuration controller and a flash memory. The EP2S60F484C3N is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed via the external flash interface after FPGA configuration is complete. The EP2S60F484C3N features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial device chain, the enhanced configuration device EP2S60F484C3N features concurrent configuration and parallel configuration.

Parametrics

EP2S60F484C3N absolute maximum ratings: (1)Supply voltage:-0.2V to 4.6V; (2)DC input voltage:-0.5V to 3.6V; (3)DC VCC or ground current:100mA; (4)DC output current, per pin:-25mA to 25mA; (5)Power dissipation:360mW; (6)Storage temperature:-65℃ to 150℃; (7)Ambient temperature:-65℃ to 135℃; (8)Junction temperature:135℃.

Features

EP2S60F484C3N features: (1)Supports ISP via Jam Standard Test and Programming Language(STAPL); (2)Supports JTAG boundary scan; (3)nINIT_CONF pin allows private JTAG instruction to start FPGA configuration; (4)Internal pull-up resistor on nINIT_CONF always enabled; (5)User programmable weak internal pull-up resistors on nCS and OE pins; (6)Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines; (7)Standby mode with reduced power consumption; (8)Supports byte-wide configuration mode fast passive parallel(FPP); 8-bit data output per DCLK cycle; (9)Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs; (10)Pin-selectable 2-ms or 100-ms power-on reset (POR) time ; (11)Configuration clock supports programmable input source and frequency synthesis; (12)Supply voltage of 3.3 V (core and I/O); (13)Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification .

Diagrams