(China (Mainland))
Product Summary
The XC2C384-10TQG144C belongs to the highly uniform family of fast, low power CPLD. The underlying architecture is a traditional CPLD architecture combining macrocells into Function Blocks (FBs) interconnected with a global routing matrix, the Xilinx Advanced Interconnect Matrix (AIM). The Function Blocks use a Programmable Logic Array (PLA) configuration which allows all product terms to be routed and shared among any of the macrocells of the FB.
Parametrics
XC2C384-10TQG144C absolute maxing ratings: (1)VCC Supply voltage relative to GND: min=-0.5V, max=2.0V; (2)VI Input voltage relative to GND: min=0.5V, max=4.0V; (3)TJ Maximum junction temperature: min=40℃, max=150℃; (4)TSTR Storage temperature: min=65℃, max=150℃.
Features
XC2C384-10TQG144C features: (1)Optimized for 1.8V systems: Industry fastest low power CPLD; Densities from 32 to 512 macrocells; (2)ndustry best 0.18 micron CMOS CPLD: Optimized architecture for effective logic synthesis; Multi-voltage I/O operation: 1.5V to 3.3V; (3)Design entry/verification using Xilinx and industry standard CAE tools; (4)Free software support for all densities using Xilinx WebPACK Industry leading nonvolatile 0.18 micron CMOS process: Guaranteed 1,000 program/erase cycles; Guaranteed 20 year data retention.
Diagrams
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 XC2C384-10TQG144C |
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IC CR-II CPLD 384MCELL 144-TQFP |
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